Refereed Journals
2020
[12]Yarui Peng, Quang Le, Imam Al Razi, Shilpi Mukherjee, Tristan Evans, and H. Alan Mantooth, "PowerSynth Progression on Layout Optimization for Reliability and Signal Integrity", IEICE Nonlinear Theory and Its Applications, vol. 11, no. 2, pp. 124-144, Apr 2020, Invited Paper. [bibtex] [doi] [PDF]
[11]Kevin Hermanns, Yarui Peng, and H. Alan Mantooth, "The Increasing Role of Design Automation in Power Electronics: Gathering What Is Needed", IEEE Power Electronics Magazine, vol. 7, no. 1, pp. 46-50, Mar 2020. [bibtex] [doi] [IEEE] [PDF]
2019
[10]Tristan Evans, Quang Le, Shilpi Mukherjee, Imam Al Razi, Tom Vrotsos, Yarui Peng, and H. Alan Mantooth, "Powersynth: A Power Module Layout Generation Tool", IEEE Transactions on Power Electronics, vol. 34, no. 6, pp. 5063–5078, Jun 2019, Highlighted Paper. [bibtex] [doi] [IEEE] [PDF]
2018
[9]Yarui Peng, Dusan Petranovic, Kambiz Samadi, Pratyush Kamal, Yang Du, and and Sung Kyu Lim, "Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs", IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 634–644, Jul 2018. [bibtex] [doi] [IEEE] [PDF]
2017
[8]Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, "Design Methodologies for Low-power 3-D ICs with Advanced Tier Partitioning", IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 7, pp. 2109–2117, Jul 2017. [bibtex] [doi] [IEEE] [PDF]
[7]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Parasitic Extraction for Heterogeneous Face-to-face Bonded 3-D ICs", IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 7, no. 6, pp. 912–924, Jun 2017. [bibtex] [doi] [IEEE] [PDF]
[6]Can Rao, Tongqing Wang, Yarui Peng, Jie Cheng, Yuhong Liu, Sung Kyu Lim, and Xinchun Lu, "Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Processing", IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 2, pp. 143–154, May 2017. [bibtex] [doi] [IEEE] [PDF]
2016
[5]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, "Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs", IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 5, pp. 1636–1648, May 2016. [bibtex] [doi] [IEEE] [PDF]
2015
[4]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 1964–1976, Dec 2015. [bibtex] [doi] [IEEE] [PDF]
[3]Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, "Fine-Grained 3-D IC Partitioning Study With a Multicore Processor", IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 10, pp. 1393–1401, Oct 2015. [bibtex] [doi] [IEEE] [PDF]
[2]Sandeep Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, "Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies", IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 7, pp. 980–990, Jul 2015. [bibtex] [doi] [IEEE] [PDF]
2014
[1]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 12, pp. 1900–1913, Dec 2014. [bibtex] [doi] [IEEE] [PDF]
Refereed Conference Papers
2020
[21]Md Arafat Kabir, and Yarui Peng, "Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools", in Proc. Asia and South Pacific Design Automation Conference, pp. 351-356, Jan 2020. [bibtex] [IEEE] [PDF]
[20]Tristan Evans, Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth, "Electronic Design Automation Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules", (accepted) in Proc. IEEE Energy Conversion Congress and Exposition, 2020. [bibtex]
[19]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, "Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization", (accepted) in Proc. IEEE Energy Conversion Congress and Exposition, 2020. [bibtex]
2019
[18]Tristan Evans, Quang Le, Balaji Narayanasamy, Yarui Peng, Fang Luo, and H. Alan Mantooth, "Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization", in Proc. IMAPS International Symposium on Microelectronics, pp. 193-198, Oct 2019. [bibtex] [doi] [PDF]
[17]Bakhtiyar Md Nafis, Ange Iradukunda, Imam Al Razi, David R. Huitink, and Yarui Peng, "System-level Thermal Management and Reliability of Automotive Electronics: Goals and Opportunities in the Next Generation of Electric and Hybrid Electric Vehicles", in Proc. ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, pp. 1-8, Oct 2019. [bibtex] [doi] [PDF]
[16]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, "Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules", in Proc. IEEE Energy Conversion Congress and Exposition, pp. 2257-2263, Sep 2019. [bibtex] [doi] [IEEE] [PDF]
2017
[15]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging", in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 1–3, Dec 2017, Best Paper Award. [bibtex] [doi] [IEEE] [PDF]
[14]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging", in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1–3, Oct 2017. [bibtex] [doi] [IEEE] [PDF]
2016
[13]Can Rao, Yarui Peng, Tongqing Wang, Sung Kyu Lim, and Xinchun Lu, "Investigation of Post-Annealing Stress and Pop-Out in TSV Front-side CMP", in Proc. International Conference on Planarization/CMP Technology, Oct 2016, Best Student Paper Award. [bibtex]
2015
[12]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs", in Proc. International Conference on Computer-Aided Design, pp. 649–655, Nov 2015. [bibtex] [doi] [IEEE] [PDF]
[11]Yarui Peng, Bon Woong Ku, Younsik Park, Kwang-Il Park, Seong-Jin Jang, Joo Sun Choi, and Sung Kyu Lim, "Design, Packaging, and Architectural Policy Co-Optimization for DC Power Integrity in 3D DRAM", in Proc. Design Automation Conference, pp. 1–6, Jun 2015. [bibtex] [doi] [IEEE] [PDF]
[10]Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, and Sung Kyu Lim, "3D IC Power Benefit Study Under Practical Design Considerations", in Proc. International Interconnect Technology Conference, pp. 335–338, May 2015. [bibtex] [doi] [IEEE] [PDF]
[9]Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, and Sung Kyu Lim, "Thermal Impact Study of Block Folding and Face-to-Face Bonding in 3D IC", in Proc. International Interconnect Technology Conference, pp. 331–334, May 2015. [bibtex] [doi] [IEEE] [PDF]
2014
[8]Sandeep Samal, Yarui Peng, and Sung Kyu Lim, "Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs", in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014. [bibtex]
[7]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs", in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014, Best in Session Award. [bibtex]
[6]Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, and Sung Kyu Lim, "On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective", in Proc. Design Automation Conference, pp. 1–6, Jun 2014. [bibtex] [doi] [IEEE] [PDF]
[5]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Fast and Accurate Full-chip Extraction and Optimization of TSV-to-wire Coupling", in Proc. Design Automation Conference, pp. 1–6, Jun 2014. [bibtex] [doi] [IEEE] [PDF]
2013
[4]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs", in Proc. International Conference on Computer-Aided Design, pp. 281–288, Nov 2013. [bibtex] [doi] [IEEE] [PDF]
[3]Sandeep Samal, Yarui Peng, Yang Zhang, and Sung Kyu Lim, "Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs", in Proc. International Symposium on Low Power Electronics and Design, pp. 21–26, Sep 2013. [bibtex] [doi] [IEEE] [PDF]
[2]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, "Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs", in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2013. [bibtex]
[1]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, "Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs", in Proc. Design Automation Conference, pp. 1–7, May 2013. [bibtex] [IEEE] [PDF]
Refereed Workshop Papers
2019
[4]Quang Le, Tristan Evans, Yarui Peng, and H. Alan Mantooth, "PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization", in Proc. IEEE International Workshop on Integrated Power Packaging, pp. 131–136, Apr 2019. [bibtex] [doi] [IEEE] [PDF]
2018
[3]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, "Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Optimization in PowerSynth", in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 323–330, Oct 2018. [bibtex] [doi] [IEEE] [PDF]
[2]Shilpi Mukherjee, Tristan Evans, Balaji Narayanasamy, Quang Le, Asif Imran Emon, Amol Deshpande, Fang Luo, Yarui Peng, Steve Pytel, Tom Vrotsos, and Alan Mantooth, "Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts", in Proc. IEEE Workshop on Control and Modeling for Power Electronics, pp. 1–8, Jun 2018. [bibtex] [doi] [PDF]
2017
[1]Quang Le, Tristan Evans, Shilpi Mukherjee, Yarui Peng, Tom Vrotsos, and H. Alan Mantooth, "Response Surface Modeling for Parasitic Extraction for Multi-Objective Optimization of Multi-Chip Power Modules (MCPMs)", in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 327–334, Oct 2017. [bibtex] [doi] [PDF]