| [18] | Quang Le, Imam Al Razi, Tristan Evans, Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth, “Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses”, IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 11, no. 6, pp. 5613-5625, 2023.
|
|---|
| [17] | Imam Al Razi, Quang Le, Tristan Evans, H. Alan Mantooth, and Yarui Peng, “PowerSynth 2: Physical Design Automation for High-Density 3D Multi-Chip Power Modules”, IEEE Transactions on Power Electronics, vol. 38, no. 4, pp. 4698-4713, 2023.
|
|---|
| [16] | David Huitink, Whit Vinson, Collin Ruby, Imam Al Razi, David Agogo-Mawuli, H. Alan Mantooth, and Yarui Peng, “Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules”, Journal of Microelectronics and Electronic Packaging, vol. 20, no. 4, pp. 107–111, 2023.
|
|---|
| [14] | Md. Arafat Kabir, and Yarui Peng, “Holistic Chiplet-Package Co-Optimization for Agile Custom 2.5D Design”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 11, no. 5, pp. 715–726, 2021.
|
|---|
| [13] | Imam Al Razi, Quang Le, Tristan Evans, Shilpi Mukherjee, H. Alan Mantooth, and Yarui Peng, “PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5D Multi-Chip Power Modules”, IEEE Transactions on Power Electronics, vol. 36, no. 8, pp. 8919–8933, 2021.
|
|---|
| [12] | Yarui Peng, Quang Le, Imam Al Razi, Shilpi Mukherjee, Tristan Evans, and H. Alan Mantooth, “PowerSynth Progression on Layout Optimization for Reliability and Signal Integrity”, IEICE Nonlinear Theory and Its Applications, vol. 11, no. 2, pp. 124–144, Apr 2020, Invited Paper.
|
|---|
| [11] | Kevin Hermanns, Yarui Peng, and H. Alan Mantooth, “The Increasing Role of Design Automation in Power Electronics: Gathering What Is Needed”, IEEE Power Electronics Magazine, vol. 7, no. 1, pp. 46–50, Mar 2020.
|
|---|
| [8] | Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, “Design Methodologies for Low-power 3-D ICs with Advanced Tier Partitioning”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 7, pp. 2109–2117, Jul 2017.
|
|---|
| [7] | Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Parasitic Extraction for Heterogeneous Face-to-face Bonded 3-D ICs”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 7, no. 6, pp. 912–924, Jun 2017.
|
|---|
| [6] | Can Rao, Tongqing Wang, Yarui Peng, Jie Cheng, Yuhong Liu, Sung Kyu Lim, and Xinchun Lu, “Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Processing”, IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 2, pp. 143–154, May 2017.
|
|---|
| [4] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 1964–1976, Dec 2015.
|
|---|
| [3] | Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, “Fine-Grained 3-D IC Partitioning Study With a Multicore Processor”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 10, pp. 1393–1401, Oct 2015.
|
|---|
| [2] | Sandeep Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, “Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 7, pp. 980–990, Jul 2015.
|
|---|