Students will study the design and implementation of a standard Reduced Instruction Set Computer (RISC) and memory hierarchy. The course offers a detailed analysis of (1) instruction set encodings, (2) efficient pipelined implementation of the instruction set including data and control hazards introduced by pipelining instruction execution, and (3) memory hierarchy including cache and virtual memory. The laboratory component allows students to apply classroom theory by designing and implementing a complete working pipelined CPU and developing functions in assembly language through a simulator.
Corequisite: Lab component
Prerequisite: CSCE2114: Digital Design (C or higher)
Required Textbook: "Computer Organization and Design MIPS Edition: The Hardware/Software Interface," by David A. Patterson and John L. Hennessy, Six Edition, Morgan Kaufmann, ISBN: 978-0128201091. Note: Zybook will be used for this class. In addition, course notes for all lectures will be used.
"Computer Architecture: A Quantitative Approach," by David A. Patterson and John L. Hennessy, Six Edition, Morgan Kaufmann, ISBN: 978-0128119051
"Computer Systems: A Programmer's Perspective," by Randal Bryant and David O'Hallaron, 3rd Edition, Pearson, ISBN: 978-0134092669
The goal of the class is to develop the skills to analyze and design both hardware and software components of a computer, and to evaluate the performance of a computer.