Computer-Aided Design (CAD), also referred to as Electronic Design Automation (EDA), uses computer software running in high-performance computing servers to design Very-Large-Scale Integrated (VLSI) Circuits, Packages, or Boards.

Modern computers benefit from Moore’s Law with an exponentially growing number of transistors and computing capabilities. State-of-the-art processors contain tens of billions of transistors per chip. However, the need for speed has never been greater. Emerging technologies such as AI, Machine Learning, Blockchain, and Smart Grid rely on these fundamental computing infrastructures to thrive. Electrical Vehicles, 5G mobile devices, and Internet-of-Things (IoT) also require energy-efficient computing power. However, the design complexity of high-performance and low-power systems has reached an unprecedented level that makes it impossible to design manually without help from computers.

Computer-Aided Design uses advanced algorithms, software tools, and AI techniques to assist hardware engineers with their design tasks. These CAD tools are used in all design steps, including modeling and simulation, circuit design and synthesis, placement and routing, analysis and optimization, verification and testing, and manufacturing. Research to enable new capabilities and integrate advanced technologies is a never-ending journey.

The Research Areas Include:

• Computer-Aided Design for VLSI Circuit, Packaging, and System Design
• Heterogeneous 2.5D/3D Chiplet Design, Integration, and Optimization
• Advanced Packaging Modeling, Analysis, and Optimization
• Power Electronics Modeling, Circuit Design, and Layout Synthesis

Our Research is Sponsored by:

• National Science Foundation
• Army Research Lab
• NSF POETS ERC

Our Current Collaborators Include: NSF POETS ERC, UA Power Group, Army Research Lab, Mentor Graphics, GTCAD Lab, National Tsinghua University, etc.

Power electronic devices play a key role to provide next generation energy conversion and transmission in mobile power systems. New materials and devices with wide-bandgap (WBG) semiconductor-based power electronics are promising solutions for high power density, high energy efficiency, high thermal resistant, and low cost advanced power electronic modules. The long term goal is to achieve 10x higher power density than current technologies on the market.

The design of Multi-Chip-Power-Modules (MCPM) requires extensive knowledge of the device, circuit, package all the way to system and manufacturing. Designers need to understand electrical and thermal properties of materials, multi-physics design procedures, system control and optimization methodology, and the engineering art of design for manufacturability and reliability. Layout design of MCPM, currently performed manually with limited optimization capabilities, takes significant time to complete. The thermal profile is only checked after the layout is finished and any unexpected hot spots may require a complete redesign.

Our research at POETS center tries to address both electrical and thermal issues altogether before the MCPM layout is finalized. An automated tool based on the PowerSynth project is developed to further enrich the layout synthesis capability by introducing new algorithms and novel optimization methods for MCPM parasitic extraction, thermal modeling, heterogeneous integration, and reliability enhancement. We also investigate automated process and design rule checking, process design kit development, and memorialized software architecture platform to create a standard MCPM design tool flow. This project also requires collaborations among other faculties and students from Uark, UIUC, Stanford and Howard, as well as industry liaisons from Toyota, Wolfspeed, Deere, Caterpillar etc.

One promising solution to extend the Moore’s Law is 3D ICs. The through-silicon-via (TSV) is used for vertical interconnection in 3D ICs and provides wide connections between the top and bottom dies. TSVs allow 3D ICs to have ultra-high density and bandwidths but much lower power consumption for data transmission. Because of increased wire and TSV density, parasitic components between TSVs and wires become important contributors to signal coupling in 3D ICs.

Unlike F2B bonding, in which the vertical interconnection density is limited by the TSV size, face-to-face (F2F) bonding technology connects top metal layers from both dies with F2F vias. They can achieve much higher three-dimensional (3D) connection density with F2F vias in a few microns which results in a much closer die-to-die distance. Such a close distance is similar to the thickness of inter-layer dielectrics (ILD) of the top metal layers, which makes parasitic extraction inaccurate without considering the electrical fields (E-fields) from the neighboring die.

The third option of integrating multiple dies is the Fan-out wafer-level-packaging (FOWLP). It provides a low-cost multi-die package solution with excellent thermal and RF properties, and extremely thin layer thicknesses using the BEOL technology. This 2.5D solution overcomes some disadvantages of 3D ICs, while still provides significant power and performance improvement over traditional 2D ICs.

The signal integrity of the 2.5D/3D IC system needs accurate parasitic extraction for reliable operation and signal transmission. Also, the power and thermal reliability need to be addressed before these emerging technologies can be widely adopted. These challenging problems call for advanced and innovative design automation algorithms, flows and methodologies for physical design, package integration, thermal and power analysis and optimization, parasitic extraction and signal integrity verification.