| [44] | Mehran Sanjabiasasi, Imam Al Razi, H. Alan Mantooth, and Yarui Peng, “A Comparative Study on Optimization Algorithms in PowerSynth 2”, in Proc. IEEE Design Methodologies Conference, pp. 1-8, Sep 2023.
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| [43] | Tristan Evans, Yarui Peng, and H. Alan Mantooth, “VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2023.
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| [42] | Zahra Saadatizadeh, Mehran Sanjabiasasi, David Agogo-Mawuli, David Huitink, Yarui Peng, and H. Alan Mantooth, “Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2023.
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| [41] | David Huitink, Whit Vinson, Collin Ruby, Imam Al Razi, David Agogo-Mawuli, Alan Mantooth, and Yarui Peng, “Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules”, in Proc. International Conference and Exhibition on High Temperature Electronics, pp. 27–31, Apr 2023.
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| [40] | Imam Al Razi, Whit Vinson, David Huitink, and Yarui Peng, “Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1-8, Oct 2022.
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| [39] | Quang Le, Md. Maksudul Hossain, Tristan Evans, Yarui Peng, and H. Alan Mantooth, “Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2022.
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| [38] | Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation”, in Proc. International Conference on Computer-Aided Design, pp. 1-8, Nov 2021.
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| [37] | Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct 2021.
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| [36] | Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “Fast and Accurate Inductance Extraction For Power Module Layout Optimization Using Loop-Based Method”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1358-1365, Oct 2021.
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| [35] | Joshua Mitchener, Imam Al Razi, and Yarui Peng, “Designing a Graphical User Interface for the Power Module Optimization Tool PowerSynth”, in Proc. ASEE Midwest Section Conference, pp. 1-12, Sep 2021.
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| [34] | Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “PowerSynth Integrated CAD Flow for High Density Power Modules”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021.
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| [33] | Tristan Evans, Yarui Peng, and H. Alan Mantooth, “Placement and Routing for Power Module Layout”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021.
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| [32] | Imam Al Razi, David Huitink, and Yarui Peng, “PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module”, in Proc. IEEE Applied Power Electronics Conference, pp. 1516-1523, Jun 2021.
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| [31] | Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design”, in Proc. ACM Great Lakes Symposium on VLSI, pp. 135–140, Jun 2021.
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| [30] | Md. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, and Yarui Peng, “Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization”, in Proc. International Symposium on VLSI Design, Automation and Test, pp. 1–4, May 2021, Invited Paper.
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| [29] | Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design”, in Proc. International Conference on Computer-Aided Design, pp. 1–8, Nov 2020.
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| [28] | Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1984–1991, Oct 2020.
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| [27] | Tristan Evans, Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth, “Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 5046–5052, Oct 2020.
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| [26] | Md. Arafat Kabir, and Yarui Peng, “Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study”, in Proc. IEEE International System-on-Chip Conference, pp. 277-282, Sep 2020.
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| [25] | Shilpi Mukherjee, Yarui Peng, and Alan Mantooth, “General Equation to Determine Design Rules for Mitigating Partial Discharge and Electrical Breakdown in Power Module Layouts”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, pp. 1–6, Sep 2020.
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| [24] | Md. Arafat Kabir, and Yarui Peng, “Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools”, in Proc. Asia and South Pacific Design Automation Conference, pp. 351–356, Jan 2020.
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| [23] | Bakhtiyar Md Nafis, Ange Iradukunda, Imam Al Razi, David Huitink, and Yarui Peng, “System-level Thermal Management and Reliability of Automotive Electronics: Goals and Opportunities in the Next Generation of Electric and Hybrid Electric Vehicles”, in Proc. ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, pp. 1–8, Oct 2019.
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| [22] | Tristan Evans, Quang Le, Balaji Narayanasamy, Yarui Peng, Fang Luo, and H. Alan Mantooth, “Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization”, in Proc. IMAPS International Symposium on Microelectronics, pp. 193–198, Oct 2019.
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| [21] | Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 2257–2263, Sep 2019.
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| [20] | Quang Le, Tristan Evans, Yarui Peng, and H. Alan Mantooth, “PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization”, in Proc. IEEE International Workshop on Integrated Power Packaging, pp. 131–136, Apr 2019.
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| [19] | Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Optimization in PowerSynth”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 323–330, Oct 2018.
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| [18] | Shilpi Mukherjee, Tristan Evans, Balaji Narayanasamy, Quang Le, Asif Imran Emon, Amol Deshpande, Fang Luo, Yarui Peng, Steve Pytel, Tom Vrotsos, and Alan Mantooth, “Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts”, in Proc. IEEE Workshop on Control and Modeling for Power Electronics, pp. 1–8, Jun 2018.
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| [17] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 1–3, Dec 2017, Best Paper Award.
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| [16] | Quang Le, Tristan Evans, Shilpi Mukherjee, Yarui Peng, Tom Vrotsos, and H. Alan Mantooth, “Response Surface Modeling for Parasitic Extraction for Multi-Objective Optimization of Multi-Chip Power Modules (MCPMs)”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 327–334, Oct 2017.
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| [15] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1–3, Oct 2017.
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| [13] | Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs”, in Proc. International Conference on Computer-Aided Design, pp. 649–655, Nov 2015.
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| [12] | Yarui Peng, Bon Woong Ku, Younsik Park, Kwang-Il Park, Seong-Jin Jang, Joo Sun Choi, and Sung Kyu Lim, “Design, Packaging, and Architectural Policy Co-Optimization for DC Power Integrity in 3D DRAM”, in Proc. Design Automation Conference, pp. 1–6, Jun 2015.
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| [11] | Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, and Sung Kyu Lim, “3D IC Power Benefit Study Under Practical Design Considerations”, in Proc. International Interconnect Technology Conference, pp. 335–338, May 2015.
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| [10] | Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, and Sung Kyu Lim, “Thermal Impact Study of Block Folding and Face-to-Face Bonding in 3D IC”, in Proc. International Interconnect Technology Conference, pp. 331–334, May 2015.
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| [9] | Sandeep Samal, Yarui Peng, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014.
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| [8] | Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014, Best in Session Award.
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| [7] | Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, and Sung Kyu Lim, “On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective”, in Proc. Design Automation Conference, pp. 1–6, Jun 2014.
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| [6] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Fast and Accurate Full-chip Extraction and Optimization of TSV-to-wire Coupling”, in Proc. Design Automation Conference, pp. 1–6, Jun 2014.
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| [5] | Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs”, in Proc. International Conference on Computer-Aided Design, pp. 281–288, Nov 2013.
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| [4] | Sandeep Samal, Yarui Peng, Yang Zhang, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, in Proc. International Symposium on Low Power Electronics and Design, pp. 21–26, Sep 2013.
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| [3] | Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, “Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2013.
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| [2] | Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, “Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs”, in Proc. Design Automation Conference, pp. 1–7, May 2013.
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