| [9] | Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation”, in Proc. International Conference on Computer-Aided Design, pp. 1-8, Nov 2021.
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| [8] | Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct 2021.
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| [7] | Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “Fast and Accurate Inductance Extraction For Power Module Layout Optimization Using Loop-Based Method”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1358-1365, Oct 2021.
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| [6] | Joshua Mitchener, Imam Al Razi, and Yarui Peng, “Designing a Graphical User Interface for the Power Module Optimization Tool PowerSynth”, in Proc. ASEE Midwest Section Conference, pp. 1-12, Sep 2021.
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| [5] | Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “PowerSynth Integrated CAD Flow for High Density Power Modules”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021.
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| [4] | Tristan Evans, Yarui Peng, and H. Alan Mantooth, “Placement and Routing for Power Module Layout”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021.
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| [3] | Imam Al Razi, David Huitink, and Yarui Peng, “PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module”, in Proc. IEEE Applied Power Electronics Conference, pp. 1516-1523, Jun 2021.
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| [2] | Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design”, in Proc. ACM Great Lakes Symposium on VLSI, pp. 135–140, Jun 2021.
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| [1] | Md. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, and Yarui Peng, “Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization”, in Proc. International Symposium on VLSI Design, Automation and Test, pp. 1–4, May 2021, Invited Paper.
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