| 2017 | |
| [3] | Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, “Design Methodologies for Low-power 3-D ICs with Advanced Tier Partitioning”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 7, pp. 2109–2117, Jul 2017. |
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| [2] | Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Parasitic Extraction for Heterogeneous Face-to-face Bonded 3-D ICs”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 7, no. 6, pp. 912–924, Jun 2017. |
| [1] | Can Rao, Tongqing Wang, Yarui Peng, Jie Cheng, Yuhong Liu, Sung Kyu Lim, and Xinchun Lu, “Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Processing”, IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 2, pp. 143–154, May 2017. |
| 2017 | |
| [3] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 1–3, Dec 2017, Best Paper Award. |
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| [2] | Quang Le, Tristan Evans, Shilpi Mukherjee, Yarui Peng, Tom Vrotsos, and H. Alan Mantooth, “Response Surface Modeling for Parasitic Extraction for Multi-Objective Optimization of Multi-Chip Power Modules (MCPMs)”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 327–334, Oct 2017. |
| [1] | Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1–3, Oct 2017. |