VLSI-CAD: VLSI Design with Advanced Packaging and Emerging Technologies

One promising solution to extend the Moore’s Law is 3D ICs. The through-silicon-via (TSV) is used for vertical interconnection in 3D ICs and provides wide connections between the top and bottom dies. TSVs allow 3D ICs to have ultra-high density and bandwidths but much lower power consumption for data transmission. Because of increased wire and TSV density, parasitic components between TSVs and wires become important contributors to signal coupling in 3D ICs.

Unlike F2B bonding, in which the vertical interconnection density is limited by the TSV size, face-to-face (F2F) bonding technology connects top metal layers from both dies with F2F vias. They can achieve much higher three-dimensional (3D) connection density with F2F vias in a few microns which results in a much closer die-to-die distance. Such a close distance is similar to the thickness of inter-layer dielectrics (ILD) of the top metal layers, which makes parasitic extraction inaccurate without considering the electrical fields (E-fields) from the neighboring die.

The third option of integrating multiple dies is the Fan-out wafer-level-packaging (FOWLP). It provides a low-cost multi-die package solution with excellent thermal and RF properties, and extremely thin layer thicknesses using the BEOL technology. This 2.5D solution overcomes some disadvantages of 3D ICs, while still provides significant power and performance improvement over traditional 2D ICs.

The signal integrity of the 2.5D/3D IC system needs accurate parasitic extraction for reliable operation and signal transmission. Also, the power and thermal reliability need to be addressed before these emerging technologies can be widely adopted. These challenging problems call for advanced and innovative design automation algorithms, flows and methodologies for physical design, package integration, thermal and power analysis and optimization, parasitic extraction and signal integrity verification.

Ongoing Projects

  1. CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs
    • Sponser: NSF CISE #2047388
    • Budget: $500,000
    • Period: 2021.6 - 2025.5
    • PI: Yarui Peng
  2. CRII: SHF: Design, Extraction, and Optimization of Multi-Chip Fan-Out Wafer-Level-Packaging for Low-Power Heterogeneous Systems
    • Sponser: NSF CISE #1755981
    • Budget: $175,000
    • Period: 2018.7 - 2023.6
    • PI: Yarui Peng