Power electronic devices play a key role to provide next generation energy conversion and transmission in mobile power systems. New materials and devices with wide-bandgap (WBG) semiconductor-based power electronics are promising solutions for high power density, high energy efficiency, high thermal resistant, and low cost advanced power electronic modules. The long term goal is to achieve 10x higher power density than current technologies on the market.

The design of Multi-Chip-Power-Modules (MCPM) requires extensive knowledge of the device, circuit, package all the way to system and manufacturing. Designers need to understand electrical and thermal properties of materials, multi-physics design procedures, system control and optimization methodology, and the engineering art of design for manufacturability and reliability. Layout design of MCPM, currently performed manually with limited optimization capabilities, takes significant time to complete. The thermal profile is only checked after the layout is finished and any unexpected hot spots may require a complete redesign.

Our research at POETS center tries to address both electrical and thermal issues altogether before the MCPM layout is finalized. An automated tool based on the PowerSynth project is developed to further enrich the layout synthesis capability by introducing new algorithms and novel optimization methods for MCPM parasitic extraction, thermal modeling, heterogeneous integration, and reliability enhancement. We also investigate automated process and design rule checking, process design kit development, and memorialized software architecture platform to create a standard MCPM design tool flow. This project also requires collaborations among other faculties and students from Uark, UIUC, Stanford and Howard, as well as industry liaisons from Toyota, Wolfspeed, Deere, Caterpillar etc.

1. PowerSynth 3D: Extending Design Automation from Modules to Converters

   • Sponser: NSF POETS ERC #R1.020.22
   • Budget: $119,316
   • Period: 2022.8 - 2024.7
   • PI: Alan Mantooth, Yarui Peng, Yue Zhao, Andrew Stillwell

1. Combined Electromigration and Mechanical Failure Risk in Interconnects: The Imminent Threat to Power Package Reliability

   NSF POETS ERC #R1.016.20, $286,584, 2020.8 - 2022.7, David Huitink, Yarui Peng and Pingfang Wang
2. Enhancing and Demonstration of PowerSynth-Integrated Physical Design Flow

   NSF POETS ERC #R1.012.19, $410,372, 2019.8 - 2022.7, Alan Mantooth, Yarui Peng
3. Integration of Thermomechanical Reliability Enhancing Technologies into High Density Module, with Design for Reliability Layout Optimization Scheme

   NSF POETS ERC #R2.025.18, $355,000, 2018.8 - 2020.7, David Huitink, Yarui Peng, Simon Ang, Nenad Miljkovic
4. High Speed Integrated 15 kV SiC MOSFET Power Module: Architecture, Design, Fabrication, and Testing

   DoD ARL #W911NF1920231, $700,000, 2018.5 - 2021.5, Fang Luo, David Huitink, Alan Mantooth, Simon Ang, Yarui Peng
5. PowerSynth Progression Towards an Infrastructure for Heterogeneous & 3D Modules

   NSF POETS ERC #R1.007.17, $265,000, 2017.8 - 2019.7, Alan Mantooth, Yarui Peng