by Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, and Xiaohang Wang
Reference:
Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, and Xiaohang Wang, “Design Challenges of Intra- and Inter- Chiplet Interconnection”, IEEE Design & Test, vol. 39, no. 6, pp. 99–109, 2022.
Bibtex Entry:
@string{mag.ieee.mdat="IEEE Design & Test"}
@Article{C.Chen-Mag.IEEE.MDAT-2022,
	author={Chixiao Chen and Jieming Yin and Yarui Peng and Maurizio Palesi and Wenxu Cao and Letian Huang and Amit Kumar Singh and Haocong Zhi and Xiaohang Wang},
	title   = {{Design Challenges of Intra- and Inter- Chiplet Interconnection}},
	journal = Mag.IEEE.MDAT,
	year    = {2022},
	ieee={9869866},
	volume={39},
  number={6},
  pages={99--109},
  doi={10.1109/MDAT.2022.3203005},
}