Dr. Peng presented a keynote [mp4] on Heterogeneous Chiplet EDA Tools at the HipChips Workshop, co-located with ISCA 2023. Slides can be found on the workshop website
Dr. Imam Al Razi has defended his Ph.D. desertation, "Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization" in 2022 July and become the first Ph.D. alumnus from E3DA Lab!
Imam joined E3DA in 2017 fall from Bangladesh University of Engineering and Technology, and worked on the PowerSynth team. He will join Intel after graduation as a CAD engineer. We wish him good luck and continued success in his future career!
The PowerSynth 2 tool, based on Imam's Ph.D. work, has been released and open sourced on github. For details, please check out our research web pages.
Dr. Peng has received the NSF Faculty Early Career Development Award in 2021, known as the NSF CAREER award.
Graduate Openings: Research Assistant
- A PH.D. GRA position in computer-aided design and analysis of multi-chip heterogenous 2.5D chiplet design is available at this time, starting from 2023 Fall. A strong background in programming and algorithm designs is required. C/C++ programming and VHDL/Verilog design skills are also required. CAD/EDA software skills (From Cadence/Synopsys/Mentor Graphics, not from CAE areas such as AutoCAD), matlab/perl/python programming, digital/analog circuit design experience and VLSI physical design experience are strongly preferred.
- A Master Thesis GRA position in computer-aided design and chiplet-package co-design is available at this time, starting from 2023 Fall. Students with a background in EE, CE, and CS are welcome to apply. Programing skills in python or matlab and knowledge in VHDL/Verilog design is required. Design experience in VLSI or circuit simulation is a plus.
- A M.S. GRA position in computer-aided design and reliability modeling/optimization for data centers is available at this time, starting from 2023 Fall. A strong background in programming and multi-physics simulation is required. Programming and software development skills are also highly encouraged. Electronics design, packaging, and power system design and simulation experiences are strongly preferred. Familiar with linux usage, VLSI design is a plus.
- Another PH.D. GRA position in power electronics converter design is available at this time, starting from 2023 Fall. It may be under ELEG major. A strong background in programming and power electronics design is required. Circuit design and simulations skills are also required. Power electronics design, packaging, and power system design and simulation experiences are strongly preferred. Familiar with linux usage, matlab or python or other programming experience is a plus.
All CSCE Ph.D RAs receive a standard monthly stipend of $1860 with a tuition waiver (Annual 15 credits) For exceptional outstanding applicants, I can recommend you for DDF and DAF fellowships from graduate school. They offer an additional annual scholarship of $22,000 (DDF) and $12,000 (DAF) for 4 years to cover your living expenses. For these fellowships, US citizens are preferred (international students can still be considered) and an early application is required (By Jan for Fall applications, and by Sep for Spring applications) and the slots are filled very quickly. All Master RAs receive a standard monthly stipend of $1464 plus the same tuition waiver as Ph.D.
Interested candidates please send me your CV and transcript for review, including your TOFEL/IELTS GRE scores as well. Make sure you have read our publications in related areas before you apply.
Undergrad Openings: Hourly Student
- Another hourly position in electro/thermal modeling and cooling solution design is available at this time, starting from 2022 Fall. Experience in related fields is strong prefered, including circuit, thermal, and stress modeling and simulation. Students from electrical engineering, computer science and computer engineering or mechanical engineering are welcome to apply. Strong math/physics background including numerical analysis and simulation skill is a plus.
Depending on the skill sets and academic levels, all hourly students will be paid at $14-15 (undergrad) $16-18 (master) hourly rate based on the committed time. I can help with your reference letter for your future education applications. A good academic standing (GPA 3.4+) is required. Getting an A in related courses with interests in our research fields are strongly prefered. If there are mutual matching interests in the research projects, RA position is also an option.
Undergrad Openings: POETS REU Student
POETS is looking for undergraduate students with research interests in power electroincs to join our research teams at UIUC, UA, Stanford, and Howard University. Should a student be selected for the REU experience, they could go to either one of those top schools and conduct research during a 10-week time frame. All exciting opportunities, which will be supported financially with travel and living expenses. Students are also funded for attendance to the annual POETS meeting where they will get to present their research.
The POETS REU website https://poets-erc.org/reu gives interested students a good overview of what to expect from the POETS REU program. Several of our previous students are supported under this program. POETS is using the NSF REU portal to accept applications this year. The actual application materials will be uploaded and submitted through this page. As the POETS site explains, although the application deadline is February 15th, spots are limited and participants will be accepted on a rolling basis, so the sooner students apply, the better their chances are of being accepted.