With heterogeneous components tightly integrated, new parasitics, resulting from both electrical- and magnetic-coupling, require both IC and package designers to work together closely on circuit and physical design. The proposed CAD framework blurs the boundaries between chip and package layouts in the design flow and extracts major coupling elements between them. It integrates chip-package co-design techniques into the entire VLSI design flow with time-efficient computational models so that signal integrity issues can be captured and addressed early to avoid a time-consuming trial-and-error design process.
Fulfulling the promise of open-sourcing our CAD framework, we deliver E3DA 2.5D Chiplet-Package Co-Design Flow, packaged with design cases and detailed step-by-step manuals. Due to the NDA requirement, some of our design files cannot be published, thus we are instead releasing sample designs based on open PDKs. More design cases will be released along with updated pacakges. New CAD tools will be available once packaged for release. Stay tuned and check back on this website as we have to carefully review and gradually release source code and design files to avoid NDA and license issues.
Our source code, design files, and manuals (this package) is published under the MIT license. The software can be evaluated and distributed for education, research, and commercial use. The University of Arkansas only requests that you attribute this work in your publications and presentations as appropriate in return for the free usage of the tool.
The software is provided "AS IS", without warranty of any kind, express or implied, including but not limited to the warranties of merchantability, fitness for a particular purpose and noninfringement. In no event shall the authors or copyright holders be liable for any claim, damages or other liability, whether in an action of contract, tort or otherwise, arising from, out of or in connection with the software or the use or other dealings in the software.
Release: In-Context 2.5D (v1.0)
In recent years, 2.5D chiplet package designs have gained popularity in system integration of heterogeneous technologies. Currently, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach does not consider any package layers during extraction and optimization, and an accurate chiplet-package extraction can not be applied to heterogeneous designs without fundamental changes in standard CAD tools. In this paper, we present our Holistic and In-Context chiplet-package co-design flows for high-performance high-density 2.5D systems using standard ASIC CAD tools with zero overhead on IO pipeline depth. Our flow encompasses 2.5D-aware partitioning, chiplet-pac-kage co-planning, in-context extraction, iterative optimization, and post-design analysis and verification of the entire 2.5D system. We design our package planner with a routing and pin-planning strategy to minimize package routing congestion and timing overhead. An ARM Cortex-M0-based microcontroller system is designed as the benchmark. The performance gap to the reference 2D design reduces by 62.5% when chip-package interactions are taken into account in the holistic flow. Our in-context extraction achieves only 0.71% and 0.79% error on ground and coupling capacitance on a homogeneous system. Further, we implement a heterogeneous 2.5D system to demonstrate our novel in-context design and optimization methodology.
Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng "Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design", International Conference on Computer-Aided Design, 2020. [PDF]
Release: Holistic 2.5D (v1.0)
With the increasing popularity and applications of 2.5D integration, both chip and packaging industries are making significant progress in this direction. In advanced high-density 2.5D packages, package redistribution layers become similar to chiplet Back-End-of-Line routing layers, and the gap between them scales down with pin density improvement. Chiplet-package interactions become significant and severely affect system performance and reliability. Moreover, 2.5D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. In this paper, we present a holistic chiplet-package co-optimization flow for high-density 2.5D packaging technologies with little performance overhead and zero pipeline-depth increase. Our holistic extraction can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Both drop-in and pay-as-you-use design methodologies are implemented for agile development and quick turn-around time. To prove the effectiveness of our flow, we implement several design cases of a microcontroller system in TSMC 65nm technology. Our design methodologies can reduce the performance gap by 85% w.r.t. the 2D reference design after holistic optimizations. We demonstrate design flexibility and development cost-saving by presenting several flavors of a three chiplets system. To validate our flow in silicon, we tape-out a chip in TSMC 65nm technology with measured data and validated functionality.
Md. Arafat Kabir and Yarui Peng "Holistic Chiplet-Package Co-Optimization for Agile Custom 2.5D Design", IEEE Transactions on Components, Packaging, and Manufacturing Technology, 2021. [PDF]
We are currently developping a new design flow for heterogeneous 2.5D systems with incremental optimization techniques. Will update once a new package is released.
For publications not associated with a specific release, please refer to the publication page for the most up-to-date publication list and downloadable pdfs.