Refereed Journals
2023
[18]Quang Le, Imam Al Razi, Tristan Evans, Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth, “Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses”, IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 11, no. 6, pp. 5613-5625, 2023. BibTex DOI IEEE PDF
[17]Imam Al Razi, Quang Le, Tristan Evans, H. Alan Mantooth, and Yarui Peng, “PowerSynth 2: Physical Design Automation for High-Density 3D Multi-Chip Power Modules”, IEEE Transactions on Power Electronics, vol. 38, no. 4, pp. 4698-4713, 2023. BibTex DOI IEEE PPT PDF
[16]David Huitink, Whit Vinson, Collin Ruby, Imam Al Razi, David Agogo-Mawuli, H. Alan Mantooth, and Yarui Peng, “Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules”, Journal of Microelectronics and Electronic Packaging, vol. 20, no. 4, pp. 107–111, 2023. BibTex DOI PDF
2022
[15]Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, and Xiaohang Wang, “Design Challenges of Intra- and Inter- Chiplet Interconnection”, IEEE Design & Test, vol. 39, no. 6, pp. 99–109, 2022. BibTex DOI IEEE PDF
2021
[14]Md. Arafat Kabir, and Yarui Peng, “Holistic Chiplet-Package Co-Optimization for Agile Custom 2.5D Design”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 11, no. 5, pp. 715–726, 2021. BibTex DOI IEEE PDF
[13]Imam Al Razi, Quang Le, Tristan Evans, Shilpi Mukherjee, H. Alan Mantooth, and Yarui Peng, “PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5D Multi-Chip Power Modules”, IEEE Transactions on Power Electronics, vol. 36, no. 8, pp. 8919–8933, 2021. BibTex DOI IEEE PDF
2020
[12]Yarui Peng, Quang Le, Imam Al Razi, Shilpi Mukherjee, Tristan Evans, and H. Alan Mantooth, “PowerSynth Progression on Layout Optimization for Reliability and Signal Integrity”, IEICE Nonlinear Theory and Its Applications, vol. 11, no. 2, pp. 124–144, Apr 2020, Invited Paper. BibTex DOI PDF
[11]Kevin Hermanns, Yarui Peng, and H. Alan Mantooth, “The Increasing Role of Design Automation in Power Electronics: Gathering What Is Needed”, IEEE Power Electronics Magazine, vol. 7, no. 1, pp. 46–50, Mar 2020. BibTex DOI IEEE PDF
2019
[10]Tristan Evans, Quang Le, Shilpi Mukherjee, Imam Al Razi, Tom Vrotsos, Yarui Peng, and H. Alan Mantooth, “Powersynth: A Power Module Layout Generation Tool”, IEEE Transactions on Power Electronics, vol. 34, no. 6, pp. 5063–5078, Jun 2019, Highlighted Paper. BibTex DOI IEEE PDF
2018
[9]Yarui Peng, Dusan Petranovic, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, “Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs”, IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 634–644, Jul 2018. BibTex DOI IEEE PDF
2017
[8]Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, “Design Methodologies for Low-power 3-D ICs with Advanced Tier Partitioning”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 7, pp. 2109–2117, Jul 2017. BibTex DOI IEEE PDF
[7]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Parasitic Extraction for Heterogeneous Face-to-face Bonded 3-D ICs”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 7, no. 6, pp. 912–924, Jun 2017. BibTex DOI IEEE PDF
[6]Can Rao, Tongqing Wang, Yarui Peng, Jie Cheng, Yuhong Liu, Sung Kyu Lim, and Xinchun Lu, “Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Processing”, IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 2, pp. 143–154, May 2017. BibTex DOI IEEE PDF
2016
[5]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, “Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1636–1648, May 2016. BibTex DOI IEEE PDF
2015
[4]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 1964–1976, Dec 2015. BibTex DOI IEEE PDF
[3]Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, “Fine-Grained 3-D IC Partitioning Study With a Multicore Processor”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 10, pp. 1393–1401, Oct 2015. BibTex DOI IEEE PDF
[2]Sandeep Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, “Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 5, no. 7, pp. 980–990, Jul 2015. BibTex DOI IEEE PDF
2014
[1]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 12, pp. 1900–1913, Dec 2014. BibTex DOI IEEE PDF
Refereed Conference Papers
2024
[44]Mehran Sanjabiasasi, H. Alan Mantooth, and Yarui Peng, “PowerSynth: Automated Power Converter Layout Synthesis with Customized Components”, (accepted) in Proc. IEEE Energy Conversion Congress and Exposition, Oct 2024. BibTex
2023
[43]Mehran Sanjabiasasi, Imam Al Razi, H. Alan Mantooth, and Yarui Peng, “A Comparative Study on Optimization Algorithms in PowerSynth 2”, in Proc. IEEE Design Methodologies Conference, pp. 1-8, Sep 2023. BibTex DOI IEEE PPT MP4
[42]Tristan Evans, Yarui Peng, and H. Alan Mantooth, “VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2023. BibTex DOI IEEE PPT MP4 PDF
[41]Zahra Saadatizadeh, Mehran Sanjabiasasi, David Agogo-Mawuli, David Huitink, Yarui Peng, and H. Alan Mantooth, “Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2023. BibTex DOI IEEE PPT PDF
[40]David Huitink, Whit Vinson, Collin Ruby, Imam Al Razi, David Agogo-Mawuli, Alan Mantooth, and Yarui Peng, “Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules”, in Proc. International Conference and Exhibition on High Temperature Electronics, pp. 27–31, Apr 2023. BibTex DOI PPT PDF
2022
[39]Imam Al Razi, Whit Vinson, David Huitink, and Yarui Peng, “Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1-8, Oct 2022. BibTex DOI IEEE PPT MP4 PDF
[38]Quang Le, Md. Maksudul Hossain, Tristan Evans, Yarui Peng, and H. Alan Mantooth, “Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Sep 2022. BibTex DOI IEEE PPT MP4 PDF
2021
[37]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation”, in Proc. International Conference on Computer-Aided Design, pp. 1-8, Nov 2021. BibTex DOI IEEE PPT MP4 PDF
[36]Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct 2021. BibTex DOI IEEE PPT MP4 PDF
[35]Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “Fast and Accurate Inductance Extraction For Power Module Layout Optimization Using Loop-Based Method”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1358-1365, Oct 2021. BibTex DOI IEEE PPT MP4 PDF
[34]Joshua Mitchener, Imam Al Razi, and Yarui Peng, “Designing a Graphical User Interface for the Power Module Optimization Tool PowerSynth”, in Proc. ASEE Midwest Section Conference, pp. 1-12, Sep 2021. BibTex DOI PPT PDF
[33]Quang Le, Imam Al Razi, Yarui Peng, and H. Alan Mantooth, “PowerSynth Integrated CAD Flow for High Density Power Modules”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021. BibTex DOI IEEE PPT MP4 PDF
[32]Tristan Evans, Yarui Peng, and H. Alan Mantooth, “Placement and Routing for Power Module Layout”, in Proc. IEEE Design Methodologies Conference, pp. 1-6, Jul 2021. BibTex DOI IEEE PPT MP4 PDF
[31]Imam Al Razi, David Huitink, and Yarui Peng, “PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module”, in Proc. IEEE Applied Power Electronics Conference, pp. 1516-1523, Jun 2021. BibTex DOI IEEE PPT MP4 PDF
[30]Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design”, in Proc. ACM Great Lakes Symposium on VLSI, pp. 135–140, Jun 2021. BibTex DOI PPT MP4 PDF
[29]Md. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, and Yarui Peng, “Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization”, in Proc. International Symposium on VLSI Design, Automation and Test, pp. 1–4, May 2021, Invited Paper. BibTex DOI IEEE PPT MP4 PDF
2020
[28]Md. Arafat Kabir, Dusan Petranovic, and Yarui Peng, “Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design”, in Proc. International Conference on Computer-Aided Design, pp. 1–8, Nov 2020. BibTex DOI IEEE PPT MP4 PDF
[27]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 1984–1991, Oct 2020. BibTex DOI IEEE PPT MP4 PDF
[26]Tristan Evans, Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth, “Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 5046–5052, Oct 2020. BibTex DOI IEEE PPT MP4 PDF
[25]Md. Arafat Kabir, and Yarui Peng, “Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study”, in Proc. IEEE International System-on-Chip Conference, pp. 277-282, Sep 2020. BibTex DOI IEEE PPT MP4 PDF
[24]Shilpi Mukherjee, Yarui Peng, and Alan Mantooth, “General Equation to Determine Design Rules for Mitigating Partial Discharge and Electrical Breakdown in Power Module Layouts”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, pp. 1–6, Sep 2020. BibTex DOI IEEE PPT MP4 PDF
[23]Md. Arafat Kabir, and Yarui Peng, “Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools”, in Proc. Asia and South Pacific Design Automation Conference, pp. 351–356, Jan 2020. BibTex DOI IEEE PPT PDF
2019
[22]Bakhtiyar Md Nafis, Ange Iradukunda, Imam Al Razi, David Huitink, and Yarui Peng, “System-level Thermal Management and Reliability of Automotive Electronics: Goals and Opportunities in the Next Generation of Electric and Hybrid Electric Vehicles”, in Proc. ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, pp. 1–8, Oct 2019. BibTex DOI PDF
[21]Tristan Evans, Quang Le, Balaji Narayanasamy, Yarui Peng, Fang Luo, and H. Alan Mantooth, “Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization”, in Proc. IMAPS International Symposium on Microelectronics, pp. 193–198, Oct 2019. BibTex DOI PPT PDF
[20]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules”, in Proc. IEEE Energy Conversion Congress and Exposition, pp. 2257–2263, Sep 2019. BibTex DOI IEEE PPT PDF
[19]Quang Le, Tristan Evans, Yarui Peng, and H. Alan Mantooth, “PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization”, in Proc. IEEE International Workshop on Integrated Power Packaging, pp. 131–136, Apr 2019. BibTex DOI IEEE PPT PDF
2018
[18]Imam Al Razi, Quang Le, H. Alan Mantooth, and Yarui Peng, “Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Optimization in PowerSynth”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 323–330, Oct 2018. BibTex DOI IEEE PPT PDF
[17]Shilpi Mukherjee, Tristan Evans, Balaji Narayanasamy, Quang Le, Asif Imran Emon, Amol Deshpande, Fang Luo, Yarui Peng, Steve Pytel, Tom Vrotsos, and Alan Mantooth, “Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts”, in Proc. IEEE Workshop on Control and Modeling for Power Electronics, pp. 1–8, Jun 2018. BibTex DOI PPT PDF
2017
[16]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 1–3, Dec 2017, Best Paper Award. BibTex DOI IEEE PPT PDF
[15]Quang Le, Tristan Evans, Shilpi Mukherjee, Yarui Peng, Tom Vrotsos, and H. Alan Mantooth, “Response Surface Modeling for Parasitic Extraction for Multi-Objective Optimization of Multi-Chip Power Modules (MCPMs)”, in Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications, pp. 327–334, Oct 2017. BibTex DOI IEEE PPT PDF
[14]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging”, in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1–3, Oct 2017. BibTex DOI IEEE PPT PDF
2016
[13]Can Rao, Yarui Peng, Tongqing Wang, Sung Kyu Lim, and Xinchun Lu, “Investigation of Post-Annealing Stress and Pop-Out in TSV Front-side CMP”, in Proc. International Conference on Planarization/CMP Technology, Oct 2016, Best Student Paper Award. BibTex
2015
[12]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs”, in Proc. International Conference on Computer-Aided Design, pp. 649–655, Nov 2015. BibTex DOI IEEE PPT PDF
[11]Yarui Peng, Bon Woong Ku, Younsik Park, Kwang-Il Park, Seong-Jin Jang, Joo Sun Choi, and Sung Kyu Lim, “Design, Packaging, and Architectural Policy Co-Optimization for DC Power Integrity in 3D DRAM”, in Proc. Design Automation Conference, pp. 1–6, Jun 2015. BibTex DOI IEEE PPT PDF
[10]Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, and Sung Kyu Lim, “3D IC Power Benefit Study Under Practical Design Considerations”, in Proc. International Interconnect Technology Conference, pp. 335–338, May 2015. BibTex DOI IEEE PDF
[9]Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, and Sung Kyu Lim, “Thermal Impact Study of Block Folding and Face-to-Face Bonding in 3D IC”, in Proc. International Interconnect Technology Conference, pp. 331–334, May 2015. BibTex DOI IEEE PPT PDF
2014
[8]Sandeep Samal, Yarui Peng, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014. BibTex
[7]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2014, Best in Session Award. BibTex PPT PDF
[6]Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, and Sung Kyu Lim, “On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective”, in Proc. Design Automation Conference, pp. 1–6, Jun 2014. BibTex DOI IEEE PDF
[5]Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, “Fast and Accurate Full-chip Extraction and Optimization of TSV-to-wire Coupling”, in Proc. Design Automation Conference, pp. 1–6, Jun 2014. BibTex DOI IEEE PPT PDF
2013
[4]Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, “On Accurate Full-chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs”, in Proc. International Conference on Computer-Aided Design, pp. 281–288, Nov 2013. BibTex DOI IEEE PPT PDF
[3]Sandeep Samal, Yarui Peng, Yang Zhang, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, in Proc. International Symposium on Low Power Electronics and Design, pp. 21–26, Sep 2013. BibTex DOI IEEE PDF
[2]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, “Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs”, in Proc. SRC TECHCON Conference, pp. 1–4, Sep 2013. BibTex
[1]Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, “Full-chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs”, in Proc. Design Automation Conference, pp. 1–7, May 2013. BibTex IEEE PDF
Thesis
2022
[3]Imam Al Razi, “Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization”, Ph.D. dissertation, University of Arkansas, Fayetteville, AR, 2022. BibTex PPT PDF
2021
[2]Md. Arafat Kabir, “Design, Extraction, and Optimization Tool Flows and Methodologies for Homogeneous and Heterogeneous Multi-Chip 2.5D Systems”, M.S. thesis, University of Arkansas, Fayetteville, AR, 2021. BibTex PPT PDF
2016
[1]Yarui Peng, “CAD Tools and Methodologies for Reliable 3D IC Design, Analysis, and Optimization”, Ph.D. dissertation, Georgia Institute of Technology, Atlanta, GA, 2016. BibTex PPT PDF